systems analysis and design

As the title said, this book has a lot of good examples on how to write VHDL code with good coding styles. Most of the good coding style tips in the book make sense and I use it in my work. However, I don't think this is a good book to learn VHDL. The syntax is explained in the same style as the VHDL Language Reference Manual, which is very dry. For example: the author explained the syntax of for loop like this: loop_statement ::= [loop_label][iteraction_scheme] loop sequence_of_statements end loop [loop_label]. I learned some VHDL constructs from this book but they are not very clear. After finished reading the book, I still feel something missing and I need to refer to other VHDL books to fill up the gap. The author also spent only a few pages on synthesis and the index is poorly organized. With all of these and combined with its ridiculous price, I would recommend to borrow the book from library if you want some tips on good coding styles. But I won't recommend to buy it if you want to learn basic VHDL, because the book is no good for that purpose.

This is the best of 4 books I purchased on the subject of VHDL, by a factor of 10. The price took me by surprise but it was readily available through the third party link. Buy this one and you won't need any of the others. If I would have purchased this one a year ago it would have saved me much grief.

This is a very good reference book for checking coding styles and syntax for VHDL. There are several books that teach the basics of how to write VHDL code, but this book shows you best practices for doing a good design in your projects. This book is a must have for anyone who wants to become a proficient VHDL designer who can produce quality designs.