general

Was sharing this book with my workmate. Found it pretty useful. I think its a great reference book to have.
It has
+ A great Index.
+ Good examples.
+ Been written by the masters of Verilog.
- A lot of words (ie some people might find it very 'wordy')

Every ASIC/FPGA designer I know has this one in there shelf. So go for it.

This book should be used only by the experienced users that can filter out problematic sections.
Major problems:
- first chapter, "recommended" by authors for university courses, is extremely chaotic (begin..end blocks are called loops, exercises ask you to use loops before introducing them, etc.)
- cover of the latest edition claims coverage of the latest Verilog standard - unfortunately it is very poor coverage: new interesting features such as libraries and configurations are not mentioned at all!
- I had to work hard during many trainings to correct bad coding styles showing in students reading this book as their first Verilog publication
- the book is grossly overpriced...

Main advantage:
- good set of examples

The claim that this book has become the standard for learning Verilog is true.
I use Verilog a lot but I still wish I had read this book before writing Verilog codes.