general

This book is suitable for its time, but the contents are more intended for Verilog models. It talks a lot about the Verilog syntax; however, the title mislead me - VERY LITTLE discussion about Verilog for Synthesis. There is only one chapter devoted to systhesis, and this chapter happens to be the LAST chapter of the book.

Don't get me wrong. This is a good book for beginners in Verilog HDL. It is a "MIX-BAG" of syntax only for understanding (NOT synthesis). After reading this book, one should be familiar with the application of Verilog for Simulation and Modeling, but one may still have to get a synthesis book or training to further utilize the power of Verilog for FPGA or ASIC design (I am an FPGA designer). I gave it 3 stars due a misleading title and the fact that only a single chapter was devoted to synthesis topic.

One topic bothers me. Why would someone use Verilog HDL to model the Transisor Level (he calls it the switch level)? Isn't this the reason SPICE programs were designed to do? Besides that, Verilog HDL is still YET to add ANALOG capabilities.

This book starts from very basic knowledge of Verilog. It assumes no prior knowledge of the language. It starts from explaining the different data types of Verilog with very clear examples. Then it shows you how to create a module and why is it important to divide your design into several modules. Then it teaches you how to create a circuit at gate level modeling. The schematics of the the code is given in the book, so you can clearly see the relationship between the schematics and its corresponding Verilog code. Then it moves to data flow modeling, again with very clear examples. After that, it moves to Behavioral Modeling. This the only book that gives me a very good understanding of always block, initial block, reg data type, and most importantly blocking and non blocking assignment. It has excellent example of how to create a state machine. The rest of the book teach you some tips that will make it easier for you to write your code. It also has some very good examples of how to create a testbench. Almost every example has its own testbench. So, you will learn how to create a testbench as you read the book from the very beginning. I only have 2 complains of the book. One is it doesn't tell you which part of the language is synthesizable until near the end of the book. Second is it doesn't tell you which part of the examples is the new features in Verilog 2001. This could be problematic if your simulator and synthesis tool does not fully support Verilog 2001. But other than that, I am fully satisfied. When I first learned Verilog, I browsed many other books. And this one is absolutely the best one. Without this book, I won't be able to finish my projects ahead of time with an A+. Good job Mr. Palnitkar!

An excellent book for a beginner like me. The first few chapter explains, the flow of the language-and helps you get a good hold.wonderful book, highly recommended.