Seeing this book brought back memories of second-year Computer Science 11 years ago where I learned the comparative virtues of the now-gone VAX computer's massively complex instruction set compared to the sleek RISC SPARC processor and its optimisation opportunities through pipelining a machine instruction's execution stages.

If the above makes no sense to you, or you'd rather not be bogged down with the mathematics of predicting branching when caching, then perhaps this is not the book for you. In fact, it's hard to imagine any casual hobbyist or home user or even the bulk of IT professionals finding much to suit their needs (let alone comprehend!), except in an academic capacity.

Don't get me wrong though - that's not to say this book is valueless, and the truth is far from it. Those who persevere will be rewarded with precise and in-depth technical discussion of modern processor designs - including the Sony PlayStation 2, the cluster that runs the Google search engine, advanced topics in multithreading, instruction-level parallelism, analysis of capacity, costs and performance of disks over two decades and so much more.

Undoubtedly, the book is highly specialised and simply will not appeal to the majority of readers, but with equal certainty it is still surely one of the leading texts in its field, retaining relevance with this updated 3rd edition. If you aspire to become a leading scientist at Intel or AMD then this book is a must.

Oh - and future students beware - chapters still conclude with exercises, but still only a handful actually have solutions presented, hence making all the others possible candidates for assignment questions!

The milestone and its third edition

Rating: 5/5

First, this is certainly not an introductory text on Computer Architectures. The authors assume that people reading it have already had an introductory class or some experience. Simply put, the book is not intended to explain how cache memory works, but to present a thourough quantitative analysis to show why and when one implementation works better than another, and what improvements have been devised recently to speed this or this other measurement.
Of course, the best choice for this book would be to have it preceeded by "Computer Organization: the HW/SW interface" (aka CO-HSI), by the same authors, since it would help to better comprehend the MIPS64 and the low-level design behind it, since CO-HSI develop an older version of the MIPS itself.

This is for sure one of the most informative books I've ever encountered both as a student and as a SW engineer. It contains an overwhelming quantity of data, tips, warnings, tecniques so that the over 1100 pages seem incredibly dense. And don't be fooled the book is "only so little": there are other seven online appendixes that can be downloaded, that will add up to more than 250 pages to the book.
As experience teaches, however, quantity does not always mean quality. Yet, it seems this doesn't apply to this book, because the quality of its content is highly informative and interesting for those involved with true CA designs.

Since the first chapter it's clear that target of the book is not a survery of CAs, but a guide through the bunch of considerations and problems a design of a new CA must cope with today. I mean today because much of the data collected and presented is binded to (and updated to) the current edition and its realease date. So covered CAs for this 3ed will feature IA-64 or Sony Playstation II among the others. Nonetheless, it would be misleading to think that next year the book will become useless. Most of the considerations the authors develop and present are quite long lasting (the usage patterns of ISAs, e.g., have incurred little change since the second edition, six years ago).

This edition presents noticeable changes, even if there's no doubt the core is that of CA-AQA 2ed. To mention a few, the first chapter is of course almost totally new since it's the most time-bounded of the book. The elder chapter four (Advanced Pipelining and Instruction Level Parallellism) has been expanded into two chapters, one dealing with Hardware approaches and one with Software approaches (and both with hybrid ones). This goes into great benefit for the reader since it seems we never get enough details on modern CAs and their complexity otherwise.
However, changes has been done even in the way of reductions, and that's especially true for the elder chapter three (Pipelining). It was a full 100 pages chapter, featuring an astonishing treatment of the topic, that has been fundamental in my class of CA II. In the 3ed edition, this chapter has been moved to a shorter appendix at the end, and I think this appendix can't compare with its predecessor (even if some of the "cut" topics have been then spread through chapters 3-4 in the 3ed).

About the exposition of the topics, the authors have built a solid way to make things clear for students and not, beginners and not on quantitative analysis. The book is full of figures, graph, citation and feature a wide bibliography at the end of the book and a reasoned set of references at the end of each chapter.

The only difficulties reading this book will arise only because of the complexity of the topics, who themselves require a fair amount of attention, not because of the language which keeps always clear and straightforward.

This said, I think the book is a fully deserved 5 stars one, with no concurrents on its kind, scope and utility. That's probabily why it has been worlwide used since its first edition.

A Thick Book

Rating: 4/5

Good collection of recent microprocessor
technologies. A good approach in
quantification of computer design. However,
does the exciting field of computer architecure
justify the sheer number of words in
the book?

The book would be a better pedagogical tool
if it is less wordy, more precise and in depth
(such as in clearer explanation of Scheduling
Branch Delay Slot, etc.)

Overall a good solid text.

Atoon